1. Field of the Invention
The present invention relates to a signal processing circuit for processing an analogue signal and, more particularly, to those for processing an output signal produced from an image sensor.
2. Brief Description of the Related Art
Up to now, an image reading apparatus, which detects an objective picture such as an original manuscript by use of an image sensor to transmit an image signal, has been known.
As the image sensors thereby used for obtaining aforesaid image signals, there exist Charge Coupled Device (referred to as xe2x80x9cCCDxe2x80x9d hereinafter)-type image sensors and Metal Oxide Semiconductor (referred to as xe2x80x9cMOSxe2x80x9d)-type image sensors. The CCD-type image sensors, which have many advantages such as a high sensitivity, a high integration density and low noise characteristics, have been particularly used.
Actually, an example of color CCD-type linear image sensors is illustrated in FIG. 6. In FIG. 6, the color CCD-type linear image sensor 1601 is formed of a three-lined color CCD-type linear image sensor, wherein three pieces of CCD chips 1602-1604 provided respectively with a red, a green and a blue (referred to as xe2x80x9cRxe2x80x9d, xe2x80x9cGxe2x80x9d and xe2x80x9cBxe2x80x9d hereinafter) on-wafer-type color filters are disposed on a silicon wafer in parallel to each other.
Because each constitution of the R, the G and the B CCD chips is common in FIG. 6, the chip constitution is described only about the R chip. A light receiving part 161 formed of photoelectric transducing elements 1-5006, which transduce the optical energy to the electric energy in response to incident luminous quantities are aligned in a row. The R, the G and the B color separation filters are provided in an on-wafer status covering the CCD sensor elements constituting the light receiving part 161. In a forefront of the light receiving part 161 formed of the CCD sensor elements aligned in a row, there exists further a light-shaded pixel which is formed by masking a pixel with an aluminium mask for shading an incident light, namely, the dummy element thereby to generate an output signal during a dark status.
Transfer gates 162 and 163 are to transfer charges, which have been accumulated in the light receiving part 161 in response to the incident luminous quantities, to CCD-type shift registers 164 and 165 when they receive a shift gate pulse PHI-TG. The charges, which have been accumulated in the pixels having odd numbers of the light receiving part 161, are transferred through the transfer gates 162 to the CCD-type shift register 164 in use for the odd-numbered pixels. On the other hand, the charges, which are accumulated in the pixels having even numbers of the light receiving part 161, are transferred through the transfer gate 163 to the CCD-type shift register 165 in use for even-numbered pixels.
The CCD-type shift registers 164 and 165 transfer the charges, which have been applied from the light receiving part 161, to an output part. The CCD-type shift registers 164 and 165 are two phase-driven by a clock signal PHI-1 (PHI-1R, PHI-1FR, PHI-1G, PHI-1FG, PHI-1B, PHI-1FB) in use for driving the odd-numbered pixels and another clock signal PHI-2 (PHI-2R, PHI-2FR, PHI-2G, PHI-2FG, PHI-2B, PHI-2FB) in use for driving the even-numbered pixels.
Furthermore, an output gate 166 is to transmit each of the pixel charges stored in the CCD-type registers 164 and 165 into output capacitive ports 167a and 167b, which are to transform the transferred charges into voltage signals. Source follower amplifiers 168a and 168b each having two stages serve as circuits which prevent noises from accompanying with output signals by reducing output impedances. The output capacitive ports 167a and 167b together with the source follower amplifiers 168a and 168b constitute a Eloating Differential Amplifier (referred to as xe2x80x9cFDAxe2x80x9d hereinafter).
Herein an output signal terminal OSBR is a signal terminal thereby detecting a signal applied from the odd-numbered pixels of the red color chip. Another output signal terminal OSAR is a signal terminal thereby detecting a signal applied from the even-numbered pixels of the red color chip. Similarly, output signal terminals OSBG, OSAG, OSBB and OSAB are respective output signal terminals thereby detecting signals respectively applied from the odd-numbered pixels and the even-numbered pixels of the green and the blue chips, respectively. On the other hand, PHI-RBR, PHI-RAR, PHI-RBG, PHI-RAG, PHI-RBB and PHI-RAB are reset pulse terminals while PHI-1R, PHI-1G, PHI-1B, PHI-2R, PHI-2G and PHI-2B are clock terminals of the CCD-type shift registers. Similarly, PHI-TGR, PHI-TGG and PHI-TGB are clock terminals of the transfer gates while PHI-ODR, PHI-ODG and PHI-ODB are drain terminals of the source follower amplifiers.
In the color image sensor 1601 constituted as mentioned above, rays of the lights incident to the light receiving part 161 are transformed into electric charges, of which quantities are proportional to the luminous energies. Those electric charges are transferred to the CCD-type shift registers 164 and 165 by applying the clock pulse PHI-TGR to the transfer gates 162 and 163, being separated into the odd-numbered image pixels and the even-numbered image pixels.
Subsequently, CCD pixel signals are applied bit by bit through the output gate 166 to the output capacitive ports 167a and 167b of the FDA in response to the driving clock pulses PHI-1 and PHI-2. The output capacitive ports 167a and 167b transform the output signals produced as the charge signals into the voltage signals, which are then transmitted respectively through the two-staged source follower amplifiers 168a and 168b and through the output terminals OSB and OSA. As mentioned above, to read-out the charges stored in the CCD-type line sensor integrated in a high density by separating into two pixel groups, wherein one has the odd numbers and another has the even numbers, reduces a reset time and a signal processing time of the pixel.
Next, a signal processing circuitry shown in FIG. 2 is used to process the ODD and EVEN image signals transmitted from aforesaid color CCD-type linear image sensor till a stage for converting into digital signals. FIG. 4 is a timing chart during signal processing in the circuitry shown in FIG. 2.
As shown in FIG. 2, an analogue signal processing system 38, which transmits its own output signal to an analogue to digital (referred to xe2x80x9cA/Dxe2x80x9d hereinafter) converter 39 by receiving the output signals produced from the CCD-type sensor 37, is constituted of correlated dual sampling circuits 40 and 41, amplifiers 58 and 59 and a multiplexer circuit 60. The two output signals, which are transmitted from the CCD-type sensor 37 and have the same phase (Herein ODD signal means an output signal produced from pixels having the odd numbers of the CCD-type sensor while EVEN signal means another output signal produced from pixels having the even numbers.), are respectively subjected to two independent and equivalent analogue signal processings until they are sequentially selected and synthesized in the multiplexer circuit 60. So the signal processing operation is described only about the circuit, which deals with the ODD signal.
As can be seen from FIG. 4, each pixel of the CCD output signal 94 has a reset period 86, a feedthrough period 87, a CCD clock component transmitting period 88 and a signal component transmitting period 89. The CCD-type sensor 37 applies the signals, which have different off-sets with respect to a reset potential 90, to each image pixel. The correlated dual sampling circuit 40 serves as a constitution which removes the off-sets and extracts precisely the signal components. This correlated dual sampling circuit 40 is composed of a sample-hold circuit 46, which performs a sampling operation by applying a control signal 61 during the feedthrough period 87, of another sample-hold circuit 49, which performs another sampling operation by applying another control signal 62 during the signal component transmitting period 89, and of a still another sample-hold circuit 53 in use for transfer, which prevents the clock component 92 included in the CCD output signal from propagating toward the following amplifier and other circuits located on the subsequent stages. A differential circuit 56 is included in the sampling circuit 40 and extracts a potential difference between two signals obtained by samplings respectively during the feedthrough period and during the signal component transmitting period. Consequently, the sampling circuit 40 eliminates unnecessary off-sets generated during the reset period to extract the precise signals by use of the differential circuit 56.
An amplifier 58 located on a subsequent stage is to amplify the output signal transmitted from the correlated dual sampling circuit 40 to a signal level adequate for a dynamic range of an input port of the A/D converter 39.
The signal processing operations have been described with reference to the ODD signal processing circuit up to now. As to the EVEN signal, the same signal processing operations are to be performed.
Finally, the multiplexer circuit 60 selects the ODD signal and the EVEN signal transmitted from the respective amplifiers, which correspond to the respective pixels, to synthesize the image signal having an one-line length of the CCD-type linear image sensor to apply the output signal to the A/D converter 39. A relative moving of the objective picture with respect to the CCD-type linear image sensor can attain the image signal of a whole area covering the objective picture.
However, the constitution, wherein the ODD signal and the EVEN signal are transmitted respectively in the same phase from the output signal of the CCD-type sensor and the multiplexer circuit re-synthesizes an image signal out of the two signals to be subject to the A/D conversion, has encountered with a problem that the selections of the ODD signal and the EVEN signal cannot be performed on the same timing. This constitution has further encountered with another problem that it is difficult to set up a duty ratio of the ODD signal component relative to the EVEN signal component to be 50:50 during the synthesis in the multiplexer circuit.
An object of the invention is to render it easily enabling to control phase shifts in plurality of image signals.
To satisfy the purposes mentioned above, an embodiment according to the present invention provides an image signal processing circuit, whereto a first image signal and a second image signal are applied, comprising:
a first correlated dual sampling circuit which samples the first image signal;
a second correlated dual sampling circuit which samples the second image signal; and
a phase shifting means which shifts a phase of the first image signal:
wherein the phase shifting means is constituted to be provided within the first correlated dual sampling circuit.
By constituting the present invention as mentioned above, the present invention makes it easily possible to adjust the phase shifts of the plurality of the image signals as well as to adjust simultaneously the amplitude levels of the image signals.